RISC-V is making moves, but how will it hit the mainstream? • The Register
Feature RISC-V has been talked up as a challenger to Arm and x86, offering an open royalty-free architecture that promises flexibility and innovation without licensing costs. But for all the noise, you’re more likely to find it buried inside IoT gadgets and obscure embedded systems than powering anything that’ll typically grab a headline.
Arm runs the mobile and embedded world, and x86 still has desktop, laptop, and server markets locked down, but RISC-V? Well, it’s still waiting to punch above its weight, but it’s gaining traction as a CPU architecture. Whether or not it will make its way into the broader marketplace and power a wider range of devices is the big question.
Nvidia has quietly folded RISC-V cores into its GPUs and SoCs, and the GPU-maker expects to ship a billion RISC-V cores across its GPUs, SoCs, and other products by the end of 2024. The most notable of Nvidia’s implementations of RISC-V is the GPU System Processor, or GSP, which essentially offloads kernel driver functions and takes care of GPU utilization within the cores.
Why RISC-V must get its messaging right on open standard vs open source
Even Qualcomm is using RISC-V in some of its devices, using RV cores in microcontroller units built within its Snapdragon processors. Qualcomm has shipped devices with around 650 million RISC-V cores to date, so the project’s architecture and cores are to be found in everyday devices – but why isn’t RISC-V the headliner?
Google pulls back
Qualcomm and Nvidia aren’t the only companies that are finding use for RISC-V and the architecture. Google had been making moves in this space – it officially supported RISC-V in the Android-specific, Linux-derived Android Common Kernel (ACK) up until May 2024 when it removed support from the ACK – a significant setback for the architecture.
Despite this, Google said it remains committed to RISC-V, and plans to enhance support in the future. It told Android Authority at the time: “Android will continue to support RISC-V. Due to the rapid rate of iteration, we are not ready to provide a single supported image for all vendors. This particular series of patches removes RISC-V support from the Android Generic Kernel Image (GKI).”
Prior to the move, the hope was that manufacturers might look at building Android devices using SoCs based on the RISC-V ISA. Removing RISC-V support from the ACK doesn’t mean no Android on RISC-V kit, but rather that any maker planning to go down this road would have to do a significant amount of coding work themselves.
Google’s temporary retreat on RISC-V is a good example of the kind of basic stumbling block that a new architecture faces on the road towards mainstream – the lack of a mature and unified ecosystem. Most are familiar with the Arm ecosystem, with Qualcomm doing its thing in the laptop market currently with Windows on Arm devices, and Arm already has a foothold in the mobile ecosystem with companies such as MediaTek using the architecture to full effect within its flagship mobiles. But where does RISC-V potentially fit into the equation?
The Google retreat from RISC-V on Android is a stark reminder that even an open architecture and the flexibility it gives designers and developers (who don’t have to cough up licensing fees) is not enough on its own to make RISC-V a viable front end mainstay in the market.
But for all of its setbacks, RISC-V continues to attract interest, especially from companies that are looking to reduce their reliance on proprietary solutions to power their devices.
The China factor
Given all of the geopolitical issues surrounding China and its push for self-contained and homegrown technology, Beijing has significantly invested in the RISC-V architecture as part of its strategic solution to stave off any reliance on foreign architecture and technologies.
Companies such as Loongson, which is a Chinese chip designer, have made use of the ISA to create RISC-V-powered systems that are used within Chinese schools. Another key example is Chinese giant Alibaba, which plans to use RISC-V within its cloud servers.
All of this has garnered the attention of the US government, and since 2023, the US government has been considering lawmakers’ requests to make it harder for China to implement RISC-V’s ISA in its designs.
RISC-V International spoke out about any potential US government moves to restrict access at the time, with then CEO Calista Redmond saying this might lead to a bifurcation of the standard and “a world of incompatible solutions.”
Quite. For RISC-V as an architecture to break into powering mainstream devices, it can’t just be about innovation – it must create an ecosystem capable of attracting chipmakers as well as manufacturers that will feel comfortable building devices using RISC-V cores, knowing apps and support are in place. Both the Arm and the x86 ecosystems have spent decades creating what we have today, building out the tools and the libraries, and enabling developer support to create applications on the architectures themselves. Bottom line: things need to work for end users.
That’s perhaps one of the biggest headaches for RISC-V and the architecture as a whole: software compatibility. While both Arm and the x86 ecosystems are extensively supported, the same can’t be said for RISC-V.
You gotta have standards
It was certainly a big moment for RISC-V in October this year when the RVA23 profile was ratified. This essentially lays out a consistent set of ISA extensions that software developers can rely on and utilize to create compatible software on RISC-V architecture. Not only does it bring features such as vector operations, floating-point, and atomic instructions, but it gives RISC-V some very much needed support for AI and machine learning workloads.
Overall the ratification of the RVA23 profile brings much needed consistency to an architecture that is looking to make a name for itself, but hasn’t been able to get there.
Despite progress, it is just the first step in tackling the broader software compatibility woes the architecture has faced for some time now. What really needs to happen for RISC-V to start gaining momentum in the mainstream is for devs to get coding so that things work on RISC-V as they do on other ecosystems.
Convincing developers (and manufacturers for that matter) to adopt RISC-V as an architecture and build apps and devices is not going to be an easy task.
Phones and PCs
The other main challenge for RISC-V is the current landscape of the market, especially the mobile market. Arm has a big slice of the smartphone market, and we’re not even talking about Apple’s dominance in this space. Every flagship smartphone basically runs on Arm cores in some shape or form, and every dev toolchain is optimized for Arm. Breaking into this market is going to be a difficult nut to crack.
Then there’s the PC market, which is dominated by x86, with both AMD and Intel holding practically all of the market share; even Qualcomm’s recent Windows on Arm push still hasn’t taken a foothold, and this is despite Microsoft’s backing. For RISC-V to even contemplate entering the PC market, it has not only got to show viable and competitive performance to what’s available on x86, it also has to have the developer support that is currently lacking.
The reality for RISC-V is that, even with government backing and niche use cases, it has a lot of ground to make up on both Arm and x86.
RISC-V breaking into the fold isn’t going to happen overnight, and it’s not going to happen quickly.
Perhaps the most important question of all is whether or not RISC-V can move quickly enough to close the gap with the competition in the next five years. Companies such as MIPS and SiFive being reliant on the RISC-V ISA within embedded systems, devices, networking, SoCs, etc are a good start.
But it still feels as if we’re waiting for that breakthrough moment for RISC-V to move in on its rivals. For now, it remains an open royalty-free architecture with plenty of promise. The new CEO will need to push to ensure developers and manufacturers pick RISC-V’s ISA for devices of the future. ®
