Japan’s Rapidus says 2nm chip tech on track for 2027 • The Register

Japanese foundry upstart Rapidus says it’s on track to begin volume production of 2nm process tech after achieving a major milestone this week.

Founded in 2022, just as the pandemic-era chip shortage was beginning to ease, Rapidus aims to offer customers a viable alternative to established players like TSMC and Samsung, who currently dominate the foundry segment.

On Friday, the foundry hopeful announced it’d moved into the prototyping for its 2nm gate-all-around (GAA) transistor structure at its IIM-1 plant in Chitose City, Hokkaido, after successfully trialing ASML’s extreme ultraviolet lithography equipment to etch the wafers back in April.

In case you’re wondering, Rapidus didn’t just skip years of semiconductor research and development to bring a 2nm process node to market on its first go. The foundational tech was licensed from IBM, which you may recall demonstrated the process node all the way back in 2021. 

As of last month, Rapidus says it’s successfully installed more than 200 pieces of semiconductor equipment at its IIM-1 plant to eventually support volume production. 

Before that can happen, the company needs to finalize what’s called a process development kit or PDK for short. This collection of design files, documentation, and tools is essential for customers to design chips for production at Rapidus facilities.

The Japanese chipmaker aims to have its first PDK available in Q1 2026, with mass production penciled in for sometime in 2027, hopefully.

That will put Rapidus roughly two years behind its main rival foundries. Both TSMC and Samsung are slated to ramp production of 2nm silicon this year. Intel, the other new kid on the foundry block, is also expected to ship its first internal chips based on its 2nm-class silicon this fall, but has reportedly struggled to find external foundry customers for process tech.

Further compounding the issue of timing, it’s not unusual for new processes to suffer from higher defect rates while the fab gets everything dialed in. This is one of the reasons we tend to see leading-edge silicon first, in things like smartphones, where the smaller die area helps to offset the higher defect rate.

Rapidus aims to avoid some of this headache by adopting what it calls a “fully single-wafer front-end process,” which involves dialing in a single wafer, making any adjustments necessary. If it passes inspection, those changes are applied to the rest of the wafers.

According to the fab, this approach allows for more data to be captured and for AI models to be trained to improve yields. The use of AI in semiconductor design has grown in recent years, with major foundries like TSMC utilizing the tech to drive down defect rates. ®